IC Chips
What is IC chips?
An integrated circuit/IC chip is a circuit in which a certain number of commonly used electronic components, such as resistors, capacitors, transistors, etc., and the wires between these components, are integrated together in a semiconductor process with a specific function.
An integrated circuit/IC chip is a miniature electronic device or component.
A process whereby the transistors, resistors, capacitors, inductors, and other components and wiring required in a circuit are interconnected together in a small piece or pieces of a semiconductor wafer or dielectric substrate and then packaged in a housing to form a miniature structure with the required circuit function.
All the components in the structure have been formed as a whole, making electronic components a big step towards miniaturization, low power consumption, intelligence, and high reliability. It is represented in the circuit by the letters “IC”.
Integrated circuits were invented by Jack Kilby (integrated circuits based on germanium (Ge)) and Robert Noyes (integrated circuits based on silicon (Si)). The majority of applications in the semiconductor industry today are silicon-based integrated circuits.
The integrated circuit is a new type of semiconductor device that was developed in the late 1950s and 1960s.
It is a semiconductor manufacturing process such as oxidation, photolithography, diffusion, epitaxy, and evaporation of aluminum, which integrates all the semiconductors, resistors, capacitors, and other components required to form a circuit with certain functions, as well as the connecting wires between them, on a small silicon wafer, and then solders and packages the electronic device in a tube housing.
There are various forms of packaging shells such as round shells, flat or double inline. Integrated circuit technology includes chip manufacturing and design technology, mainly in terms of processing equipment, processing technology, packaging and testing, mass production, and the ability to design innovations.
Features of IC chips
Integrated circuits, or microcircuits, microchips, and IC chips are a way of miniaturizing circuits (mainly semiconductor devices, but also passive components, etc.) in electronics and are usually manufactured on the surface of semiconductor wafers.
Integrated circuits have the advantages of small size, lightweight, few lead wires and soldering points, long life, high reliability, and good performance, as well as low cost and easy mass production.
It is widely used not only in industrial and civil electronic equipment such as recorders, televisions, and computers, but also in military, communication, and remote control applications.
With the use of integrated circuits to assemble electronic equipment, its assembly density than the transistor can be increased by dozens to thousands of times, the stability of the equipment can also be greatly improved working time.
Types of IC chips
Integrated circuits, also known as ICs, can be divided into three categories: analog ICs, digital ICs, and mixed digital/analog ICs, depending on their function and structure.
Analogue ICs, also known as linear circuits, are used to generate, amplify and process various analog signals (signals whose amplitude varies with time.
For example, the audio signal of a semiconductor radio, the tape signal of a VCR, etc.), the input signal, and the output signal are proportional to each other.
Digital integrated circuits are used to generate, amplify and process a variety of digital signals (meaning signals that take discrete values in time and amplitude.
Examples include 5G mobile phones, digital cameras, computer CPUs, audio signals, and video signals for logic control and playback of digital TVs).
Integrated Circuit Chip Fabrication Processes
Integrated circuits can be divided into semiconductor integrated circuits and film integrated circuits according to the fabrication process.
Film ICs are also classified as thick film ICs and thin-film ICs.
Classification of Integrated Circuit chips
Integrated circuits can be classified according to their level of integration.
SSIC: Small Scale Integrated circuits (SSIC)
MSIC: Medium Scale Integrated circuits (MSIC)
LSIC: Large Scale Integrated circuits
VLSIC: Very Large Scale Integrated circuits
ULSIC: Ultra Large Scale Integrated circuits
GSICS: Very Large Scale Integrated Circuits or Ultra Large Scale Integrated Circuits (Giga Scale Integration).
IC chips are classified by conductivity type
IC chips can be classified by conductivity type into bipolar ICs and unipolar ICs, both of which are digital ICs.
Bipolar ICs are complex and consume more power, and are represented by TTL, ECL, HTL, LST-TL, and STTL. Unipolar ICs are simple to produce and consume less power, so they are easy to make into large-scale ICs, representing CMOS, NMOS, PMOS, and other types of IC
Type of IC chips by applications
IC chips can be classified according to the use of integrated circuits for television, audio ICs, video disc player ICs, video recorder ICs, computer (microcomputer) ICs, electronic piano ICs, communication ICs, camera ICs, remote control ICs, language ICs, integrated circuits for alarms and various special ICs.
1. Integrated circuits for televisions include line and field scanning ICs, center-play ICs, companion ICs, color decoding ICs, AV/TV conversion ICs, switching power supply ICs, remote control ICs, sound decoding ICs, picture-in-picture processing ICs, microprocessor (CPU) ICs, memory ICs, etc.
2. Audio ICs include AM/FM high and medium frequency circuits, stereo decoding circuits, audio pre-amplification circuits, audio operational amplification ICs, audio power amplification ICs, surround sound processing ICs, level driving ICs, electronic volume control ICs, delay reverberation ICs, electronic switching ICs, etc.
3. Video disc player ICs include system control ICs, video coding ICs, MPEG decoding ICs, audio signal processing ICs, sound effect ICs, RF signal processing ICs, digital signal processing ICs, servo ICs, motor drive ICs, etc.
4. Integrated circuits for video recorders include system control ICs, servo ICs, drive ICs, audio processing ICs and video processing ICs.
5. Computer integrated circuits, including central control unit (CPU), internal memory, external memory, I/O control circuits, etc.
6. Communication IC chips
7. Specialist control IC chips
Type of Integrated Circuit chips by uses
IC chips can be classified by application area into standard general-purpose ICs and special-purpose ICs.
Type of IC chips by shape
IC chips can be classified by shape into a round (metal casing transistor package type, generally suitable for high power), flat (good stability, small size), and double inline type.
Meaning of each part of the IC type
C-Compliant with national standards
T-TTL circuit
54S20-Schottky dual 4-input & non-gate
M – 55~125°C
D-Multi-layer ceramic double in-line package
1. BGA (ball grid array)
Ball contact array, one of the surface-mount type packages.
Ball bumps are made on the back of the printed substrate in an array pattern to replace the pins, and the LSI chip is assembled on the front of the printed substrate and then sealed with a molded resin or potting method.
Also known as a bump array carrier (PAC). Pins can exceed 200 and is a type of package used for multi-pin LSI.
The package body can also be made smaller than a QFP (quad side pin flat package).
For example, a 360-pin BGA with 1.5mm pin centers is only 31mm square, while a 304-pin QFP with 0.5mm pin centers is 40mm square. And BGAs do not have to worry about pin deformation as QFPs do.
2. BQFP (quad flat package with bumper)
A quad flat package with a bumper, one of the QFP packages that have bumps (bumper pads) at the four corners of the package body to prevent the pins from bending and deforming during transport.
US semiconductor manufacturers use this package mainly in circuits such as microprocessors and ASICs. The pin centers are 0.635mm apart and the number of pins ranges from 84 to around 196 (see QFP).
3. C-(ceramic)
A notation indicating a ceramic package. For example, CDIP stands for ceramic DIP, a notation that is often used in practice.
4. Cerdip
A ceramic double in-line package sealed with glass, used in circuits such as ECL RAM, DSP (Digital Signal Processor), etc. Cerdip with a glass window is used for UV erasable EPROMs and microcomputer circuits with EPROMs inside, etc.
The pin centers are 2.54mm apart and the number of pins ranges from 8 to 42. In Japan, this package is known as DIP-G (G means glass sealed).
5. Cerquad
One of the surface-mount packages, a ceramic QFP with an under-seal, is used to package logic LSI circuits such as DSPs.
Cerquad with a window is used to package EPROM circuits. Heat dissipation is better than plastic QFPs, allowing 1.5 to 2W of power under natural air cooling conditions.
The package cost is 3 to 5 times higher than the plastic QFP. Pin centres are available in 1.27mm, 0.8mm, 0.65mm, 0.5mm, 0.4mm and more. The number of pins ranges from 32 to 368.
Ceramic chip carrier with pins, one of the surface-mount packages, with pins leading from the four sides of the package in a zigzag shape. The windowed version is used to package UV-erasable EPROMs and microcomputer circuits with EPROMs, for example. This package is also known as QFJ, QFJ-G (see QFJ).
6. COB (chip on board)
Chip on board packaging is one of the bare chip mounting technology, semiconductor chips are cross-mounted on the printed circuit board, the electrical connection between the chip and the substrate is realized by the lead stitching method, the electrical connection between the chip and the substrate is realized by the lead stitching method, and covered with resin to ensure reliability.
Although COB is the simplest bare chip mounting technology, its packaging density is far inferior to TAB and flip-chip soldering technology.
7. DFP (dual flat package)
It is an alias for SOP (see SOP). It used to be called this but was largely abandoned in the late 1980s.
8. DIC (dual in-line ceramic package)
An alias for ceramic DIP (with glass seal) (see DIP).
9. DIL (dual in-line)
Alias for DIP (see DIP). Most European semiconductor manufacturers use this name.
10. DIP (dual in-line package)
Double in-line package. One of the cartridge packages, with pins leading out from both sides of the package, is plastic or ceramic.
DIP is the most popular cartridge package and is used in applications such as standard logic ICs, memory LSIs, and microcomputer circuits. The pin centers are 2.54mm apart and the number of pins ranges from 6 to 64.
The width of the package is usually 15.2mm and some packages with a width of 7.52mm and 10.16mm are referred to as skinny DIP and slim DIP (narrow-body DIP) respectively. In most cases, however, no distinction is made and they are simply referred to as DIPs.
In addition, ceramic DIPs sealed with low melting point glass are also called cerdip (see cerdip).
11. DSO (dual small out-lint)
An alias for SOP (see SOP). Some semiconductor manufacturers use this name.
12．DICP (dual tape carrier package)
DICP is one of the TCP (tape carrier packages). The pins are made on insulating tape and lead out from both sides of the package. Due to the use of TAB (automatic tape carrier soldering) technology, the package profile is very thin. It is commonly used for LCD driver LSIs, but most are custom-made.
In addition, a 0.5mm thick memory LSI booklet package is in the development stage. In Japan, the DICP is named DTP according to the EIAJ (Electronic Industries and Machinery Association of Japan) standard.
13. DIP (dual tape carrier package)
As above. The name of DTCP is given in the EIAJ standard (see DTCP).
14. FP (flat package)
Flat package. An alternative name for QFP or SOP (see QFP and SOP), one of the surface-mount packages. Some semiconductor manufacturers use this name.
15. Flip-chip
Flip-chip. A bare-chip packaging technique in which a metal bump is made in the electrode area of the LSI chip and then the metal bump is soldered to the electrode area on the printed substrate.
Flip-chip is the smallest and thinnest of all packaging technologies.
If the coefficient of thermal expansion of the substrate is different from that of the LSI chip, a reaction will occur at the joint, which will affect the reliability of the connection. It is therefore necessary to reinforce the LSI chip with resin and to use a substrate material with approximately the same coefficient of thermal expansion.
16. FQFP (fine pitch quad flat package)
A QFP with a pin center distance of less than 0.65 mm (see QFP). Some conductor manufacturers use this name.
17. CPAC (globe top pad array carrier)
An alternative name for BGAs (see BGA) is from Motorola, USA.
18. CQFP (quad fiat package with guard ring)
Quad fiat package with guard ring. In one of the plastic QFPs, the pins are masked with a protective resin ring to prevent bending and distortion.
Before assembling the LSI on the printed substrate, the pins are cut off from the guard ring and made into a seagull wing shape (L-shape). The pin centers are 0.5 mm apart and the maximum number of pins is around 208.
19. H-(with heat sink)
Indicates a mark with a heat sink. For example, HSOP means SOP with a heat sink.
20．Pin grid array (surface mount type)
Surface mount type PGAs are usually cartridge type packages with a pin length of approximately 3.4 mm. surface mount PGAs have a display of pins on the underside of the package with a length ranging from 1.5 mm to 2.0 mm. mounting is done by bump-soldering to a printed substrate, hence the name bump-soldered PGA.
Since the pin centers are only 1.27mm apart, half the size of cartridge PGAs, the package body can be made smaller and the number of pins is higher than cartridge types (250 to 528), making it a large scale logic LSI package.
The package substrates are multilayer ceramic substrates and glass-epoxy printed substrates. Packages made on multilayer ceramic substrates are already in use.
21. JLCC (J-leaded chip carrier)
J-shaped pin chip carrier. Alias for windowed CLCC and windowed ceramic QFJ (see CLCC and QFJ). The name is used by some semiconductor manufacturers.
22. LCC (Leadless chip carrier)
Leadless chip carrier. A surface-mount package in which only the four sides of the ceramic substrate are in contact with the electrodes and there are no pins. It is a package for high-speed and high-frequency ICs, also known as ceramic QFN or QFN-C (see QFN).
23. LGA (land grid array)
Contact display package. This is a package with an array of state-of-the-art electrode contacts on the bottom side. When assembled, it can be inserted into a socket.
Ceramic LGAs with 227 contacts (1.27 mm center pitch) and 447 contacts (2.54 mm center pitch) are now available for high-speed logic LSI circuits.
Compared to QFPs, LGAs can accommodate more input and output pins in a smaller package. In addition, due to the low impedance of the leads, they are suitable for high-speed LSI.
24. LOC (lead on chip)
One of the LSI packaging technologies, lead on-chip is a structure where the front end of the lead frame is above the chip and a solder bump is made near the center of the chip, and the electrical connection is made with lead stitching.
Compared to the original structure where the lead frame is placed near the side of the chip, the chip can be accommodated in the same size package up to about 1mm wide.
25. LQFP (low profile quad flat package)
This is the name used by the Japan Electronics Machinery Industry Association (JEMIAH) for a QFP with a package body thickness of 1.4mm, based on the new QFP form factor specifications.
26. L-QUAD
One of the ceramic QFPs. The package substrate is made of aluminum nitride, which has a thermal conductivity 7 to 8 times higher than that of aluminum oxide and has better heat dissipation. The frame of the package is made of aluminum oxide and the chip is sealed by the potting method, thus keeping costs down.
L-QUAD is a package developed for logic LSIs that can accommodate W3 power under natural air cooling conditions. The 208-pin (0.5mm center pitch) and 160-pin (0.65mm center pitch) packages for LSI logic have been developed and have been in mass production since October 1993.
27. MCM (multi-chip module)
Multi-chip module. A package in which multiple bare semiconductor chips are assembled on a single wiring substrate. Depending on the substrate material, there are three main categories: MCM-L, MCM-C, and MCM-D.
MCM-L is a component that uses the usual glass epoxy resin multilayer printed substrate. The density of the wiring is not very high and the cost is low.
MCM-C is a component using thick-film technology to form multilayer wiring with ceramic (alumina or glass-ceramic) as the substrate, similar to thick-film hybrid ICs using multilayer ceramic substrates. There are no significant differences between the two. The wiring density is higher than that of the MCM-L.
The MCM-D is a multilayer wiring using thin-film technology with ceramic (alumina or aluminum nitride) or Si or Al as substrates. The wiring density is the highest of the three types of components, but the cost is also high.
28. MFP (mini flat package)
Small flat package. Alias for plastic SOP or SSOP (see SOP and SSOP). The name is used by some semiconductor manufacturers.
29. MQFP (metric quad flat package)
A classification of QFPs according to the JEDEC (Joint Electronic Devices Committee) standard. It refers to a standard QFP with a pin center distance of 0.65mm and a body thickness of 3.8mm to 2.0mm (see QFP).
30. MQUAD (metal quad)
A QFP package developed by Olin Corporation, USA. The base plate and cover are made of aluminum and sealed with adhesive. It allows for 2.5W to 2.8W of power under natural air cooling conditions. Production started in 1993 under license from Nippon Shinko Kogyo.
31. MSP (mini square package)
QFI is an alternative name for QFI (see QFI), which was mostly called MSP in the early stages of development, and is the name prescribed by the Japan Electronics Machinery Industry Association.
34. OPMAC (over-molded pad array carrier)
Molded resin sealed bump display carrier. The name used by Motorola in the USA for molded resin sealed BGAs (see BGA).
32. P-(plastic)
A notation indicating a plastic package. For example, PDIP means plastic DIP.
33. PAC (pad array carrier)
Bump display carrier, an alias for BGA (see BGA).
34. PCLP (printed circuit board leadless package)
Printed circuit board leadless package. The name used by Fujitsu Japan for the plastic QFN (plastic LCC) (see QFN). Pin
Pin centers are available in 0.55mm and 0.4mm sizes.
35. PFPF (plastic flat package)
Plastic flat package. Alias for plastic QFP (see QFP). The name is used by some LSI manufacturers.
36. PGA (pin grid array)
Pin grid array package. A cartridge-type package in which the vertical pins on the bottom side are arranged in a display pattern. The base material is basically a multilayer ceramic substrate.
Where the material is not specifically named, it is mostly ceramic PGAs, which are used for high-speed, large-scale logic LSI circuits. The cost is high. The pin centers are typically 2.54mm apart and the pin count ranges from 64 to around 447.
To reduce costs, the package substrate can be replaced by a glass-epoxy printed substrate. Plastic PGAs with 64 to 256 pins are also available.
There is also a short-pin surface-mount PGA (touch-solder PGA) with a pin center distance of 1.27mm. (See surface mount PGA).
37. Piggyback
A packaged package. A ceramic package with sockets, similar in shape to DIP, QFP and QFN. Used in the development of devices with microcomputers to evaluate program verification operations.
For example, the EPROM is inserted into the socket for debugging. These packages are largely customized and are not widely available on the market.
38. PLCC (plastic leaded chip carrier)
Plastic chip carrier with leads. One of the surface-mount packages. The pins are led out from the four sides of the package in a zigzag shape and are made of plastic.
The pin centers are 1.27 mm apart and the number of pins ranges from 18 to 84. J-shaped pins are less deformable and easier to handle than QFPs, but cosmetic inspection after soldering is more difficult.
PLCC is similar to LCC (also known as QFN). Previously, the only difference between the two was that the former was made of plastic and the latter of ceramic.
Nowadays there are J-pin packages made of ceramic and pinless packages made of plastic (marked as plastic LCC, PC LP, P-LCC, etc.), which are no longer distinguishable.
For this reason, in 1988 the JEC decided to call packages with J-pins on all four sides QFJ and packages with electrode bumps on all four sides QFN (see QFJ and QFN).
39. P-LCC (plastic leadless chip carrier) (plastic leaded chip carrier)
Sometimes an alias for plastic QFJ, sometimes an alias for QFN (plastic LCC) (see QFJ and QFN). Some LSI manufacturers use PLCC for leaded packages and P-LCC for leadless packages to show the difference.
40. QFH (quad flat high package)
A quad flat high package with thick pins on all sides. A type of plastic QFP in which the body is made thicker to prevent breakage of the package body (see QFP). The name is used by some semiconductor manufacturers.
41. QFI (quad flat I-leaded package)
Quad flat I-leaded package. One of the surface-mount packages. The pins are led from the four sides of the package and are I-shaped downwards. Also known as MSP (see MSP). The mount is touch-soldered to the printed substrate.
The pin centers are 1.27mm apart and the number of pins ranges from 18 to 68.
42. QFJ (quad flat J-leaded package)
Quad flat J-leaded package. One of the surface-mount packages. The pins are led from the four sides of the package in a downward J-shape. This is the name given by the Japan Electrical and Mechanical Manufacturers’ Association. Pin centres are 1.27mm apart.
There are two types of material: plastic and ceramic. Plastic QFJs are mostly called PLCCs (see PLCC) and are used in circuits such as microcomputers, gate displays, DRAMs, ASSPs, OTPs, etc. The pin count ranges from 18 to 84.
Ceramic QFJs is also known as CLCC, JLCC (see CLCC). Windowed packages for UV-erase EPROMs and microcomputer chip circuits with EPROMs. Pin counts range from 32 to 84.
43. QFN (quad flat non-leaded package)
Quad flat non-leaded package. One of the surface-mount packages mostly called LCC in the late 1990s, QFN is the name prescribed by the Japan Electrical and Mechanical Manufacturers’ Association.
The package is equipped with electrode contacts on all four sides and has a smaller footprint and lower height than a QFP because it has no pins.
When stresses arise between the printed substrate and the package, they cannot be relieved at the electrode contacts. The electrode contacts are therefore not as numerous as the pins of the QFP, generally ranging from 14 to 100.
There are two types of material: ceramic and plastic. When the LCC mark is present, the QFN is basically a ceramic QFN with electrode contact centers spaced 1.27 mm apart.
The plastic QFN is a low-cost package on a glass-epoxy printed substrate. In addition to 1.27mm, there are also 0.65mm and 0.5mm electrode contact centers. These packages are also known as plastic LCC, PCLC, P-LCC, etc.
44. QFP (quad flat package)
Quad flat package. One of the surface-mount packages with pins leading out from the four sides in a seagull wing (L) shape. There are three types of substrate: ceramic, metal, and plastic.
In terms of quantity, plastic packages make up the majority. The plastic QFP is the most popular multi-pin LSI package.
They are used not only for digital logic LSI circuits such as microprocessors and gate displays but also for analog LSI circuits such as VTR signal processing and audio signal processing.
The pin centres are 1.0mm, 0.8mm, 0.65mm, 0.5mm, 0.4mm, 0.3mm, etc. The maximum number of pins in the 0.65mm center pitch is 304.
In Japan, QFPs with a pin center distance of less than 0.65mm are called QFPs (FP). However, after 2000, the Japan Electronics Machinery Industry Association (JEMIA) re-evaluated the form factor of QFPs.
Instead of distinguishing between pin center distances, the package body is divided into QFP (2.0mm to 3.6mm thick), LQFP (1.4mm thick), and TQFP (1.0mm thick) depending on the thickness of the package body.
In addition, some LSI manufacturers refer to QFPs with 0.5mm pin centers as shrink QFPs or SQFPs or VQFPs. However, some manufacturers also refer to QFPs with 0.65mm and 0.4mm pin centers as SQFPs, making the names slightly confusing.
The disadvantage of QFPs is that the pins tend to bend when the pin centers are less than 0.65mm apart. To prevent pin distortion, several improved QFP variants have emerged.
e.g. BQFP with tree finger cushions at the four corners of the package (see BQFP).
GQFPs with a protective resin ring covering the front of the pins (see GQFP).
TPQFP (see TPQFP), where test bumps are provided in the package body and can be tested by placing it in a special fixture to prevent pin deformation.
For logic LSI, many developments and high-reliability products are packaged in multilayer ceramic QFPs. Ceramic QFPs with a minimum pin center distance of 0.4 mm and a maximum pin count of 348 are also available in glass sealed versions (see Gerqa d).
45. QFP (FP) (QFP fine pitch)
The name was given by the JEM standard. It refers to QFPs with a pin center pitch of 0.55mm, 0.4mm, 0.3mm, etc. less than 0.65mm (see QFP).
46. QIC (quad in-line ceramic package)
Alias for ceramic QFP. The name is used by some semiconductor manufacturers (see QFP, Cerquad).
47. QIP (quad in-line plastic package)
Alias for plastic QFP. The name is used by some semiconductor manufacturers (see QFP).
48. QTCP (quad tape carrier package)
One of the TCP packages in which the pins are formed on an insulating tape and lead out from the four sides of the package. It is a thin package using TAB technology (see TAB, TCP).
49. QTP (quad tape carrier package)
The quad tape carrier package. The name used in the form factor for QTCP was established by the Japan Electrical Machinery Manufacturers’ Association in April 1993 (see TCP).
50. QUIL (quad in-line)
Alias for QUIP (see QUIP).
51. QUIP (quad in-line package)
A quad in-line package with four rows of pins. The pins are led from both sides of the package and are staggered and bent downwards every other one to form four rows. The pin centers are 1.27mm apart and become 2.5mm apart when inserted into a printed substrate, so they can be used in standard printed circuit boards.
A smaller package than the standard DIP. Available in ceramic and plastic. A number of pins 64.
52. SDIP (shrink dual in-line package)
A shrink dual in-line package, which is the same shape as a DIP, but with a smaller pin center distance (1.778 mm) than a DIP (2.54 mm). Hence the name.
The number of pins ranges from 14 to 90, also known as SH-DIP. There are two types of material: ceramic and plastic.
53. SH-DIP (shrink dual in-line package)
The same name as SDIP, used by some semiconductor manufacturers.
54. SIL (single in-line)
An alias for SIP (see SIP). The name SIL is mostly used by European semiconductor manufacturers.
55．SIMM (single in-line memory module)
Single in-line memory module. A memory module with electrodes near only one side of the printed substrate.
Usually refers to a component that is inserted into a socket. Standard SIMMs are available with 30 electrodes at 2.54mm centers and 72 electrodes at 1.27mm centers.
SIMMs containing 1 and 4 megabit DRAMs in SOJ packages on one or both sides of a printed substrate are widely used in personal computers, workstations, and other devices. At least 30-40% of DRAM is assembled in SIMMs.
56. SIP (single in-line package)
Single in-line package. The pins are led out from one side of the package and arranged in a straight line.
When assembled on a printed substrate, the package stands on its side.
The pin centers are usually 2.54mm apart and the number of pins ranges from 2 to 23, with most being customized.
The shape of the package varies. Some packages with the same shape as a ZIP are also called SIPs.
57. SK-DIP (skinny dual in-line package)
A type of DIP. It refers to a narrow DIP with a width of 7.62mm and a pin center distance of 2.54mm and is commonly referred to as a DIP (see DIP).
58. SL-DIP (slim dual in-line package)
A type of DIP. It refers to a narrow DIP with a width of 10.16mm and a pin center distance of 2.54mm and is commonly referred to as DIP.
59. SMD (surface mount devices)
Surface mount devices. Occasionally, some semiconductor manufacturers refer to SOPs as SMDs (see SOP).
An alias for SOP. This alias is used by many semiconductor manufacturers around the world. (See SOP).
60. SOI (small out-line I-leaded package)
Small out-line I-shaped package. One of the surface-mount packages. This package is used by Hitachi for its analog ICs (motor drive ICs). A number of pins 26.
61. SOIC (small outline integrated circuit)
An alternative name for SOP (see SOP). Many foreign semiconductor manufacturers have adopted this name.
62. SOJ (Small Out-Line J-Leaded Package)
J-shaped pins small outline package. One of the surface mount type packages. The pins are led downwards from both sides of the package in a J shape, hence the name. Usually, plastic is mostly used in memory LSI circuits such as DRAM and SRAM, but mostly DRAM.
Many DRAM devices in SO J packages are assembled on SIMMs. The pin centers are 1.27mm apart and the number of pins ranges from 20 to 40 (see SIMM).
63. SQL (Small Out-Line L-leaded package)
The name used for SOPs is in accordance with the JEDEC (Joint Electronic Devices Engineering Council) standard (see SOP).
64. SONF (Small Out-Line Non-Fin)
SOP without heat sink, same as normal SOP. The NF (non-fin) designation has been intentionally added to indicate the difference in power IC packages without a heat sink. The name is used by some semiconductor manufacturers (see SOP).
65. SOP (small Out-Line package)
Small Outline Package. One of the surface-mount packages, with pins leading out from both sides of the package in the shape of seagull wings (L-shaped). There are two types of material: plastic and ceramic. Also known as SOL and DFP.
SOPs are used not only for memory LSIs but also for less large circuits such as ASSPs. SOP is the most popular surface mount package in areas where the input and output terminals do not exceed 10 to 40. The pin centers are 1.27mm apart and the number of pins ranges from 8 to 44.
SOPs with a pin center distance of less than 1.27mm is also known as SSOPs; SOPs with an assembly height of less than 1.27mm are also known as TSOPs (see SSOP, TSOP). There is also a type of SOP with a heat sink.
66. SOW (Small Outline Package (Wide-Jype))
A name used by some semiconductor manufacturers for wide-body SOPs.
What are electronic chips made of?
From the 1930s onwards, semiconductors from the chemical elements of the periodic table were considered by researchers such as William Shockley at Bell Labs to be the most likely raw material for solid-state vacuum tubes.
From copper oxide to germanium to silicon, the raw materials were systematically studied in the 1940s and 1950s.
Today, monocrystalline silicon is the dominant base for integrated circuits, although some III-V compounds from the periodic table such as gallium arsenide are used for special applications such as light-emitting diodes, lasers, solar cells, and the fastest integrated circuits.
The method of creating defect-free crystals has taken decades.
The semiconductor IC process, which consists of the following steps, is repeated.
Yellow light (micro shading)
Etching
Thin film
Diffusion
CMP
Single crystal silicon wafers (or Group III-V, such as GaAs) are used as the base layer. Components such as MOSFETs or BJTs are then made using micro-etching, diffusion, and CMP techniques, followed by micro-etching, thin-film, and CMP techniques to make wires. Depending on the performance and cost of the product, there are aluminum and copper processes.
IC chips consist of a number of overlapping layers, each of which is defined by image technology and is usually represented by a different color.
Some layers indicate where different dopants are diffused into the base layer (becoming the diffusion layer), some define where additional ions are instilled (the instillation layer), some define the conductors (polysilicon or metal layers) and some define the connections between the conduction layers (vias or contact layers). All components consist of a specific combination of these layers.
In a self-aligning (CMOS) process, all gate layers (polysilicon or metal) form transistors where they cross the diffusion layer.
The resistive structure, the aspect ratio of the resistive structure, combined with the surface resistance coefficient, determines the resistance.
Capacitive structures, where only very small capacitances can be generated on the IC due to size restrictions.
More rarely, inductive structures can be produced as chip-carrying inductors or simulated by a cyclotron.
Because CMOS devices only direct current to transition between logic gates, CMOS devices consume much less current than dual-level components.
Random-access memory is the most common type of integrated circuit, so the highest density devices are memories, but even microprocessors have memory on them.
Despite the complexity of the structure – the width of the chip has been decreasing for decades – the layers of the integrated circuit are still much thinner than the width. The fabrication of component layers is very much like the photographic process.
Although light waves in the visible spectrum cannot be used to expose the component layers because they are too large. High-frequency photons (usually ultraviolet light) are used to create the pattern of each layer.
Each feature is so small that an electron microscope is a necessary tool for a process engineer who is debugging a manufacturing process.
Each device is tested before it is packaged using automatic test equipment (ATE). The testing process is called wafer testing or wafer probing. Wafers are cut into rectangular blocks, each called a “die”. Each good die is attached to the package by soldering aluminum or gold wires to ‘pads’, which are usually on the sides of the die.
After packaging, the device is finalized on the same or similar ATE used in the wafer probe pass.
C&T RF Antennas Inc is the IC chips supplier in China, we provide a large scale of IC chips and modules, contact us for more IC chips modules details.